The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 16, 2013

Filed:

Oct. 25, 2011
Applicants:

Chien-liang Chen, Taoyuan County, TW;

Ya-nan Mou, Hsinchu, TW;

Yuan-hui Chen, Hsinchu, TW;

Yu-jen Chang, Hsinchu County, TW;

Inventors:

Chien-Liang Chen, Taoyuan County, TW;

Ya-Nan Mou, Hsinchu, TW;

Yuan-Hui Chen, Hsinchu, TW;

Yu-Jen Chang, Hsinchu County, TW;

Assignee:

United Microelectronics Corp., Science-Based Industrial Park, Hsin-Chu, TW;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03L 7/06 (2006.01);
U.S. Cl.
CPC ...
Abstract

A charge pump circuit includes a first comparator, a PMOS tuner, a first current mirror, a first NMOS transistor, a first PMOS switch, an NMOS tuner, a second current mirror, a first PMOS transistor and a first NMOS switch. The first PMOS switch is coupled between the PMOS tuner and a first output PMOS transistor of the first current mirror, thus the parasitic capacitor formed between the gate and the drain of the first PMOS switch, the parasitic capacitor formed between the gate and the source of the first output PMOS transistor, and the parasitic capacitor formed between the gate and the drain of the first output PMOS transistor are equivalently coupled in series, lowering the capacitance between the PMOS tuner and the charge pump output, and reducing the clock feed through and the charge injection effect in the charge pump circuit.


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