The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 16, 2013
Filed:
May. 04, 2011
Veeraraghavan S. Basker, Schenectady, NY (US);
Kangguo Cheng, Schenectady, NY (US);
Bruce B. Doris, Brewster, NY (US);
Johnathan E. Faltermeier, Delanson, NY (US);
Sivananda K. Kanakasabapathy, Niskayuna, NY (US);
Hemant Adhikari, Chicago, IL (US);
Veeraraghavan S. Basker, Schenectady, NY (US);
Kangguo Cheng, Schenectady, NY (US);
Bruce B. Doris, Brewster, NY (US);
Johnathan E. Faltermeier, Delanson, NY (US);
Sivananda K. Kanakasabapathy, Niskayuna, NY (US);
Hemant Adhikari, Chicago, IL (US);
International Business Machines Corporation, Armonk, NY (US);
Globalfoundries Inc., Grand Cayman, KY;
Abstract
A method of fabricating a semiconductor device that includes at least two fin structures, wherein one of the at least two fin structures include epitaxially formed in-situ doped second source and drain regions having a facetted exterior sidewall that are present on the sidewalls of the fin structure. In another embodiment, the disclosure also provides a method of fabricating a finFET that includes forming a recess in a sidewall of a fin structure, and epitaxially forming an extension dopant region in the recess that is formed in the fin structure. Structures formed by the aforementioned methods are also described.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile