The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 02, 2013
Filed:
Apr. 17, 2009
Frank Armbruster, Erfurt, DE;
Sandeep Pagey, Noida, IN;
F. Erich Marschner, Ellicott City, MD (US);
Dan Leibovich, Modiin, IL (US);
Alok Jain, New Delhi, IN;
Axel Scherer, Beverly, MA (US);
Yaron Peri-glass, Raanana, IL (US);
Frank Armbruster, Erfurt, DE;
Sandeep Pagey, Noida, IN;
F. Erich Marschner, Ellicott City, MD (US);
Dan Leibovich, Modiin, IL (US);
Alok Jain, New Delhi, IN;
Axel Scherer, Beverly, MA (US);
Yaron Peri-Glass, Raanana, IL (US);
Cadence Design Systems, Inc., San Jose, CA (US);
Abstract
A method and apparatus for producing a verification of digital circuits are provided. In an exemplary embodiment on the invention, a plurality of verification scopes of an integrated circuit design as defined as part of a verification plan. A plurality of verification runs are executed within two or more verification scopes defined by the verification plan. At least two verification runs are selected to merge verification results together. Like named scenarios are merged together for each verification scope to generate merged verification results that are then stored into a merge database. A verification report is generated for the integrated circuit design from the merged verification results. A merge point may be specified so like named subtrees and subgroups may be merged across different verification scopes of selected verification runs. The merge point may combine check and coverage results obtained during simulation with check and coverage results obtained during formal verification.