The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 02, 2013
Filed:
Oct. 20, 2008
Hiroshi Ohtsuki, Okazaki, JP;
Mitsutaka Katada, Hoi-gun, JP;
Nobuhiko Noto, Annaka, JP;
Hiroshi Takeno, Annaka, JP;
Kazuhiko Yoshida, Chikuma, JP;
Hiroshi Ohtsuki, Okazaki, JP;
Mitsutaka Katada, Hoi-gun, JP;
Nobuhiko Noto, Annaka, JP;
Hiroshi Takeno, Annaka, JP;
Kazuhiko Yoshida, Chikuma, JP;
DENSO CORPORATION, Kariya, JP;
Shin-Etsu Handotai Co., Ltd., Tokyo, JP;
Abstract
In a SOI structure semiconductor device using a SOI substrate, a lattice distortion layer is formed by implanting Ar ions into a silicon substrate as an active layer. The lattice distortion layer is capable of serving as a gettering site. The dose amount of Ar ions is adjusted in such a manner that tensile stress in the lattice distortion layer is equal to or greater than 11 MPa and equal to or less than 27 MPa. Thus, the lattice distortion layer can prevent occurrence of a leakage current while serving as the gettering site.