The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 26, 2013

Filed:

Nov. 30, 2009
Applicants:

Timothy Antesberger, Vestal, NY (US);

Frank D. Egitto, Binghamton, NY (US);

Voya R. Markovich, Endwell, NY (US);

William E. Wilson, Waverly, NY (US);

Inventors:

Timothy Antesberger, Vestal, NY (US);

Frank D. Egitto, Binghamton, NY (US);

Voya R. Markovich, Endwell, NY (US);

William E. Wilson, Waverly, NY (US);

Assignee:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/40 (2006.01);
U.S. Cl.
CPC ...
Abstract

An electronic package for interconnecting a high density pattern of conductors of an electronic device (e.g., semiconductor chip) of the package and a less dense pattern of conductors on a circuitized substrate (e.g., PCB), the package including in one embodiment but a single thin dielectric layer (e.g., Kapton) with a high density pattern of openings therein and a circuit pattern on an opposing surface which includes both a high density pattern of conductors and a less dense pattern of conductors. Conductive members are positioned in the openings to electrically interconnect conductors of the electronic device to conductors of the circuitized substrate when the package is positioned thereon. In another embodiment, the interposer includes a second dielectric layer bonded to the first, with conductive members extending through the second layer to connect to the less dense pattern of circuitized substrate conductors. Circuitized substrate assemblies using the electronic packages of the invention are also provided.


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