The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 12, 2013
Filed:
Jul. 29, 2011
Jin-aun NG, Hsinchu, TW;
Wen-chin Yang, Miaoli, TW;
Chien-liang Chen, Hsinchu, TW;
Chung-hua Fei, Hsinchu, TW;
Maxi Chang, Banciao, TW;
Bao-ru Young, Zhubei, TW;
Harry Chuang, Hsinchu, TW;
Jin-Aun Ng, Hsinchu, TW;
Wen-Chin Yang, Miaoli, TW;
Chien-Liang Chen, Hsinchu, TW;
Chung-Hua Fei, Hsinchu, TW;
Maxi Chang, Banciao, TW;
Bao-Ru Young, Zhubei, TW;
Harry Chuang, Hsinchu, TW;
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Abstract
The present disclosure provides a method including forming STI features in a silicon substrate, defining a first and a second active regions for a PFET and an NFET, respectively; forming a hard mask having an opening to expose the silicon substrate within the first active region; etching the silicon substrate through the opening to form a recess within the first active region; growing a SiGe layer in the recess such that a top surface of the SiGe layer within the first active region and a top surface of the silicon substrate within the second active region are substantially coplanar; forming metal gate material layers; patterning the metal gate material layers to form a metal gate stack on the SiGe layer within the first active region; and forming an eSiGe S/D stressor distributed in both the SiGe layer and the silicon substrate within the first active region.