The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 05, 2013
Filed:
Mar. 21, 2006
Mukta Ghate Farooq, Hopewell Junction, NY (US);
Jasvir Singh Jaspal, Poughkeepsie, NY (US);
William Francis Landers, Wappingers Falls, NY (US);
Thomas E. Lombardi, Poughkeepsie, NY (US);
Hai Pham Longworth, Poughkeepsie, NY (US);
H. Bernhard Pogge, Hopewell Junction, NY (US);
Roger A. Quon, Rhinebeck, NY (US);
Mukta Ghate Farooq, Hopewell Junction, NY (US);
Jasvir Singh Jaspal, Poughkeepsie, NY (US);
William Francis Landers, Wappingers Falls, NY (US);
Thomas E. Lombardi, Poughkeepsie, NY (US);
Hai Pham Longworth, Poughkeepsie, NY (US);
H. Bernhard Pogge, Hopewell Junction, NY (US);
Roger A. Quon, Rhinebeck, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A system and method comprises depositing a dielectric layer on a substrate and depositing a metal layer on the dielectric layer. The system and method further includes depositing a high temperature diffusion barrier metal cap on the metal layer. The system and method further includes depositing a second dielectric layer on the high temperature diffusion barrier metal cap and the first dielectric layer, and etching a via into the second dielectric layer, such that the high temperature diffusion barrier metal cap is exposed. The system and method further includes depositing an under bump metallurgy in the via, and forming a C4 ball on the under bump metallurgy layer.