The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 29, 2013
Filed:
Jan. 28, 2011
Qingguo Wu, Vancouver, WA (US);
James S. Sims, Tigard, OR (US);
Mandyam Sriram, Beaverton, OR (US);
Seshasayee Varadarajan, Lake Oswego, OR (US);
Haiying Fu, Camas, WA (US);
Pramod Subramonium, Salem, OR (US);
Jon Henri, West Linn, OR (US);
Sirish Reddy, Hillsboro, OR (US);
Qingguo Wu, Vancouver, WA (US);
James S. Sims, Tigard, OR (US);
Mandyam Sriram, Beaverton, OR (US);
Seshasayee Varadarajan, Lake Oswego, OR (US);
Haiying Fu, Camas, WA (US);
Pramod Subramonium, Salem, OR (US);
Jon Henri, West Linn, OR (US);
Sirish Reddy, Hillsboro, OR (US);
Novellus Systems, Inc., San Jose, CA (US);
Abstract
Transistor architectures and fabrication processes generate channel strain without adversely impacting the efficiency of the transistor fabrication process while preserving the material quality and enhancing the performance of the resulting transistor. Transistor strain is generated is PMOS devices using a highly compressive post-salicide amorphous carbon capping layer applied as a blanket over on at least the source and drain regions. The stress from this capping layer is uniaxially transferred to the PMOS channel through the source-drain regions to create compressive strain in PMOS channel.