The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 15, 2013
Filed:
Jan. 19, 2011
Hong-chen Cheng, Hsinchu, TW;
Chih-chieh Chiu, Toufen, TW;
Hsu-shun Chen, Toufen, TW;
Chung-ji LU, Fongyuan, TW;
Cheng Hung Lee, Hsinchu, TW;
Hung-jen Liao, Hsin-Chu, TW;
Hong-Chen Cheng, Hsinchu, TW;
Chih-Chieh Chiu, Toufen, TW;
Hsu-Shun Chen, Toufen, TW;
Chung-Ji Lu, Fongyuan, TW;
Cheng Hung Lee, Hsinchu, TW;
Hung-Jen Liao, Hsin-Chu, TW;
Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;
Abstract
A SRAM system includes: a SRAM cell array coupled between high and low supply nodes, a difference therebetween defining a data retention voltage (VDR) for a low power data retention mode; a main power switch coupling one of high and low supply nodes to a main power supply and disconnecting the one high and low supply nodes from the main power supply during the low power data retention mode; a monitor cell including a SRAM cell preloaded with a data bit and configured for data destruction responsive to a reduction in VDR before data destruction occurs in the SRAM cell array; and a clamping power switch responsive to data destruction in the monitor cell to couple the one of the high and low supply nodes to the main power supply.