The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 01, 2013
Filed:
Jan. 12, 2011
Daniel C. Edelstein, White Plains, NY (US);
Matthew E. Colburn, Hopewell Junction, NY (US);
Edward C. Cooney, Iii, Jericho, VT (US);
Timothy J. Dalton, Ridgefield, CT (US);
John A. Fitzsimmons, Poughkeepsie, NY (US);
Jeffrey P. Gambino, Westford, VT (US);
Elbert E. Huang, Tarrytown, NY (US);
Michael W. Lane, Cortlandt Manor, NY (US);
Vincent J. Mcgahay, Poughkeepsie, NY (US);
Lee M. Nicholson, Katonah, NY (US);
Satyanarayana V. Nitta, Poughquag, NY (US);
Sampath Purushothaman, Yorktown Heights, NY (US);
Sujatha Sankaran, Wappingers Falls, NY (US);
Thomas M. Shaw, Peekskill, NY (US);
Andrew H. Simon, Fishkill, NY (US);
Anthony K. Stamper, Williston, VT (US);
Daniel C. Edelstein, White Plains, NY (US);
Matthew E. Colburn, Hopewell Junction, NY (US);
Edward C. Cooney, III, Jericho, VT (US);
Timothy J. Dalton, Ridgefield, CT (US);
John A. Fitzsimmons, Poughkeepsie, NY (US);
Jeffrey P. Gambino, Westford, VT (US);
Elbert E. Huang, Tarrytown, NY (US);
Michael W. Lane, Cortlandt Manor, NY (US);
Vincent J. McGahay, Poughkeepsie, NY (US);
Lee M. Nicholson, Katonah, NY (US);
Satyanarayana V. Nitta, Poughquag, NY (US);
Sampath Purushothaman, Yorktown Heights, NY (US);
Sujatha Sankaran, Wappingers Falls, NY (US);
Thomas M. Shaw, Peekskill, NY (US);
Andrew H. Simon, Fishkill, NY (US);
Anthony K. Stamper, Williston, VT (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
Method of manufacturing a structure which includes the steps of providing a structure having an insulator layer with at least one interconnect, forming a sub lithographic template mask over the insulator layer, and selectively etching the insulator layer through the sub lithographic template mask to form sub lithographic features spanning to a sidewall of the plurality of interconnects.