The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 01, 2013

Filed:

Jan. 19, 2011
Applicants:

Anthony G. Domenicucci, New Paltz, NY (US);

Shreesh Narasimha, Beacon, NY (US);

Karen A. Nummy, Newburgh, NY (US);

Viorel C. Ontalus, Danbury, CT (US);

Yun-yu Wang, Poughquag, NY (US);

Inventors:

Anthony G. Domenicucci, New Paltz, NY (US);

Shreesh Narasimha, Beacon, NY (US);

Karen A. Nummy, Newburgh, NY (US);

Viorel C. Ontalus, Danbury, CT (US);

Yun-Yu Wang, Poughquag, NY (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method of forming a semiconductor device includes implanting an amorphizing species into a crystalline semiconductor substrate, the substrate having a transistor gate structure formed thereupon. Carbon is implanted into amorphized regions of the substrate, with specific implant conditions tailored such that the peak concentration of carbon species coincides with the end of the stacking faults, where the stacking faults are created during the recrystallization anneal. The implanted carbon pins partial dislocations so as to prevent the dislocations from disassociating from the end of the stacking faults and moving to a region in the substrate directly below the transistor gate structure. This removes the defects, which cause device leakage fail.


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