The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 18, 2012
Filed:
Nov. 01, 2010
Sanford Chu, Singapore, SG;
Yisuo LI, Singapore, SG;
Guowei Zhang, Singapore, SG;
Purakh Raj Verma, Singapore, SG;
Sanford Chu, Singapore, SG;
Yisuo Li, Singapore, SG;
Guowei Zhang, Singapore, SG;
Purakh Raj Verma, Singapore, SG;
GLOBALFOUNDRIES Singapore Pte. Ltd., Singapore, SG;
Abstract
First example embodiments comprise forming a stress layer over a MOS transistor (such as a LDMOS Tx) comprised of a channel and first, second and third junction regions. The stress layer creates a stress in the channel and the second junction region of the Tx. Second example embodiments comprise forming a MOS FET and at least a dummy gate over a substrate. The MOS is comprised of a gate, channel, source, drain and offset drain. At least one dummy gate is over the offset drain. A stress layer is formed over the MOS and the dummy gate. The stress layer and the dummy gate improve the stress in the channel and offset drain region.