The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 11, 2012

Filed:

Oct. 28, 2009
Applicants:

Kuang-hsiung Chen, Taoyuan County, TW;

Pao-ming Hsieh, Hsinchu County, TW;

Yuan-chang Su, Taoyuan County, TW;

Shih-fu Huang, Hsinchu County, TW;

Bernd Karl Appelt, Gulf Breeze, FL (US);

Inventors:

Kuang-Hsiung Chen, Taoyuan County, TW;

Pao-Ming Hsieh, Hsinchu County, TW;

Yuan-Chang Su, Taoyuan County, TW;

Shih-Fu Huang, Hsinchu County, TW;

Bernd Karl Appelt, Gulf Breeze, FL (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/04 (2006.01);
U.S. Cl.
CPC ...
Abstract

A semiconductor package includes a patterned metal foil, a chip, wires, a patterned dielectric layer, an adhesive layer, and a molding compound. The patterned metal foil has a first surface and a second surface opposite thereto. The patterned dielectric layer is disposed on the second surface and has openings exposing at least a portion of the patterned metal foil to form joints for external electrical connection. The chip is disposed on the first surface. The adhesive layer is disposed between the chip and the patterned metal foil. The wires respectively connect the chip and the patterned metal foil. The patterned dielectric layer is located below intersections between the wires and the patterned metal foil. The patterned dielectric layer, the wires, and the patterned metal foil overlap with one another on a plane. The molding compound is disposed on the first surface and covers the chip and the wires.


Find Patent Forward Citations

Chen, Kuang-Hsiung. (2012). Semiconductor package (U.S. Patent No. 8330267). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8330267

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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