The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 13, 2012
Filed:
Jul. 30, 2008
Byung Tai DO, Singapore, SG;
Stephen A. Murphy, San Jose, CA (US);
Yaojian Lin, Singapore, SG;
Heap Hoe Kuan, Singapore, SG;
Pandi Chelvam Marimuthu, Singapore, SG;
Hin Hwa Goh, Singapore, SG;
Byung Tai Do, Singapore, SG;
Stephen A. Murphy, San Jose, CA (US);
Yaojian Lin, Singapore, SG;
Heap Hoe Kuan, Singapore, SG;
Pandi Chelvam Marimuthu, Singapore, SG;
Hin Hwa Goh, Singapore, SG;
STATS ChipPAC, Ltd., Singapore, SG;
Abstract
A semiconductor wafer contains a plurality of semiconductor die. The wafer has contact pads formed over its surface. A passivation layer is formed over the wafer. A stress buffer layer is formed over the passivation layer. The stress buffer layer is patterned to expose the contact pads. A metal layer is deposited over the stress buffer layer. The metal layer is a common voltage bus for the semiconductor device in electrical contact with the contact pads. An adhesion layer, barrier layer, and seed layer is formed over the wafer in electrical contact with the contact pads. The metal layer is mounted to the seed layer. Solder bumps or other interconnect structures are formed over the metal layer. A second passivation layer is formed over the metal layer. In an alternate embodiment, a wirebondable layer can be deposited over the metal layer and wirebonds connected to the metal layer.