The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 23, 2012

Filed:

Jan. 20, 2011
Applicants:

Masaru Kito, Yokohama, JP;

Ryota Katsumata, Yokohama, JP;

Yoshiaki Fukuzumi, Yokohama, JP;

Masaru Kidoh, Komae, JP;

Hiroyasu Tanaka, Tokyo, JP;

Hideaki Aochi, Kawasaki, JP;

Yasuyuki Matsuoka, Yokohama, JP;

Inventors:

Masaru Kito, Yokohama, JP;

Ryota Katsumata, Yokohama, JP;

Yoshiaki Fukuzumi, Yokohama, JP;

Masaru Kidoh, Komae, JP;

Hiroyasu Tanaka, Tokyo, JP;

Hideaki Aochi, Kawasaki, JP;

Yasuyuki Matsuoka, Yokohama, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01);
U.S. Cl.
CPC ...
Abstract

A non-volatile semiconductor storage device has a plurality of memory strings with a plurality of electrically rewritable memory cells connected in series. Each of the memory strings includes: a memory columnar semiconductor extending in a direction perpendicular to a substrate; a tunnel insulation layer contacting the memory columnar semiconductor; a charge accumulation layer contacting the tunnel insulation layer and accumulating charges; a block insulation layer contacting the charge accumulation layer; and a plurality of memory conductive layers contacting the block insulation layer. The lower portion of the charge accumulation layer is covered by the tunnel insulation layer and the block insulation layer.


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