The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 02, 2012
Filed:
Dec. 23, 2009
Mihir K. Roy, Chandler, AZ (US);
Islam A. Salama, Chandler, AZ (US);
Charavana K. Gurumurthy, Higley, AZ (US);
Robert L. Sankman, Phoenix, AZ (US);
Mihir K. Roy, Chandler, AZ (US);
Islam A. Salama, Chandler, AZ (US);
Charavana K. Gurumurthy, Higley, AZ (US);
Robert L. Sankman, Phoenix, AZ (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Methods for forming an integrated circuit chip package having through mold vias in a polymer block, and such packages are described. For example, a first interconnect layer may be formed on a molded polymer block, wherein the first interconnect layer comprises first interconnects through a first polymer layer and to the block. Then, at least one second interconnect layer may be formed on the first interconnect layer, wherein the second interconnect layer comprises second interconnects through a second polymer layer and to the first interconnects of the first interconnect layer. Through mold vias may then be formed through the block, into the first interconnect layer, and to the first interconnects. The through mold vias may be filled with solder to form bumps contacting the first interconnects and extending above the block. Other embodiments are also described and claimed.