The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 25, 2012

Filed:

Jun. 09, 2009
Applicants:

Peter Wung Lee, Saratoga, CA (US);

Fu-chang Hsu, San Jose, CA (US);

Hsing-ya Tsao, San Jose, CA (US);

Inventors:

Peter Wung Lee, Saratoga, CA (US);

Fu-Chang Hsu, San Jose, CA (US);

Hsing-Ya Tsao, San Jose, CA (US);

Assignee:

Aplus Flash Technology, Inc., San Jose, CA (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 11/34 (2006.01); G11C 11/4193 (2006.01);
U.S. Cl.
CPC ...
Abstract

An apparatus and method for operating an array of NOR connected flash nonvolatile memory cells erases the array in increments of a page, block, sector, or the entire array while minimizing operational disturbances and providing bias operating conditions to prevent gate to source breakdown in peripheral devices. The apparatus has a row decoder circuit and a source decoder circuit for selecting the nonvolatile memory cells for providing biasing conditions for reading, programming, verifying, and erasing the selected nonvolatile memory cells while minimizing operational disturbances and preventing gate to source breakdown in peripheral devices.


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