The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 18, 2012
Filed:
May. 19, 2010
Liang-gi Yao, Hsinchu, TW;
Chun-hu Cheng, Hsinchu, TW;
Chen-yi Lee, Keelung, TW;
Jeff J. Xu, Jhubei, TW;
Clement Hsingjen Wann, Carmel, NY (US);
Liang-Gi Yao, Hsinchu, TW;
Chun-Hu Cheng, Hsinchu, TW;
Chen-Yi Lee, Keelung, TW;
Jeff J. Xu, Jhubei, TW;
Clement Hsingjen Wann, Carmel, NY (US);
Abstract
A method for reducing interfacial layer (IL) thickness for high-k dielectrics and metal gate stack is provided. In one embodiment, the method includes forming an interfacial layer on a semiconductor substrate, etching back the interfacial layer, depositing a high-k dielectric material over the interfacial layer, and forming a metal gate over the high-k dielectric material. The IL can be chemical oxide, ozonated oxide, thermal oxide, or formed by ultraviolet ozone (UVO) oxidation process from chemical oxide, etc. The etching back of IL can be performed by a Diluted HF (DHF) process, a vapor HF process, or any other suitable process. The method can further include performing UV curing or low thermal budget annealing on the interfacial layer before depositing the high-k dielectric material.