The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 11, 2012
Filed:
Jan. 11, 2007
Anthony Dip, Cedar Creek, TX (US);
John Gumpher, Cedar Park, TX (US);
Allen John Leith, Mountain Top, PA (US);
Seungho OH, Austin, TX (US);
Anthony Dip, Cedar Creek, TX (US);
John Gumpher, Cedar Park, TX (US);
Allen John Leith, Mountain Top, PA (US);
Seungho Oh, Austin, TX (US);
Tokyo Electron Limited, Tokyo, JP;
Abstract
A method is provided for reduced defect such as void free or reduced void Si or SiGe deposition in a micro-feature on a patterned substrate. The micro-feature includes a sidewall and the patterned substrate contains an isolation layer on the field area and on the sidewall and bottom of the micro-feature. The method includes forming a Si or SiGe seed layer at the bottom of the micro-feature, and at least partially filling the micro-feature from the bottom up by selectively growing Si or SiGe onto the Si or SiGe seed layer. According to one embodiment, the Si or SiGe seed layer is formed by depositing a conformal Si or SiGe layer onto the patterned substrate, removing the Si or SiGe layer from the field area, heat treating the Si or SiGe layer in the presence of Hgas to transfer at least a portion of the Si or SiGe layer from the sidewall to the bottom of the micro-feature, and etching Si or SiGe residue from the field area and the sidewall.