The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 28, 2012

Filed:

May. 15, 2008
Applicants:

Jeffery W. Janzen, Boise, ID (US);

Russell D. Slifer, Legal Representative, Boide, ID (US);

Michael Chaine, Boise, ID (US);

Kyle K. Kirby, Eagle, ID (US);

William M. Hiatt, Eagle, ID (US);

Inventors:

Jeffery W. Janzen, Boise, ID (US);

Russell D. Slifer, legal representative, Boide, ID (US);

Michael Chaine, Boise, ID (US);

Kyle K. Kirby, Eagle, ID (US);

William M. Hiatt, Eagle, ID (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/70 (2006.01); H01L 23/02 (2006.01); H01L 23/52 (2006.01);
U.S. Cl.
CPC ...
Abstract

Pass-through 3D interconnects and microelectronic dies and systems of stacked dies that include such interconnects to disable electrical connections are disclosed herein. In one embodiment, a system of stacked dies includes a first microelectronic die having a backside, an interconnect extending through the first die to the backside, an integrated circuit electrically coupled to the interconnect, and a first electrostatic discharge (ESD) device electrically isolated from the interconnect. A second microelectronic die has a front side coupled to the backside of the first die, a metal contact at the front side electrically coupled to the interconnect, and a second ESD device electrically coupled to the metal contact. In another embodiment, the first die further includes a substrate carrying the integrated circuit and the first ESD device, and the interconnect is positioned in the substrate to disable an electrical connection between the first ESD device and the interconnect.


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