The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 14, 2012

Filed:

Feb. 18, 2010
Applicants:

Satoshi Itaya, Tokyo, JP;

Satoshi Isa, Tokyo, JP;

Mitsuaki Katagiri, Tokyo, JP;

Dai Sasaki, Tokyo, JP;

Inventors:

Satoshi Itaya, Tokyo, JP;

Satoshi Isa, Tokyo, JP;

Mitsuaki Katagiri, Tokyo, JP;

Dai Sasaki, Tokyo, JP;

Assignee:

Elpida Memory, Inc., Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01R 9/00 (2006.01); H01L 23/02 (2006.01);
U.S. Cl.
CPC ...
Abstract

A semiconductor device reduces the impedance of a wiring for supplying the circuit excluding a data output circuit with a power source voltage or a ground voltage and of speedup of data signal transmission in the data output circuit. Additional substratesare on the upper surface of semiconductor chip. First additional wiring layer for power sourceand first additional wiring layer for groundformed on respective additional substratesform prescribed conductive areas on semiconductor chip. First power source wiringCor first ground wiringCare interconnected through additional wiring layersand. Second power source wiringCand second ground wiringC, which is extended in the same direction as with DQ system signal wiringC, forms a feedback current path. Second power source wiringCand second ground wiringCare disposed adjacent to DQ system signal wiringC.


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