The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 14, 2012

Filed:

Jan. 27, 2008
Applicants:

Karan Kacker, Atlanta, GA (US);

Douglas O. Powell, Endicott, NY (US);

David L. Questad, Hopewell Junction, NY (US);

David J. Russell, Owego, NY (US);

Sri M. Sri-jayantha, Ossining, NY (US);

Inventors:

Karan Kacker, Atlanta, GA (US);

Douglas O. Powell, Endicott, NY (US);

David L. Questad, Hopewell Junction, NY (US);

David J. Russell, Owego, NY (US);

Sri M. Sri-Jayantha, Ossining, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/04 (2006.01); H01L 23/48 (2006.01); H01L 23/52 (2006.01); H01L 29/40 (2006.01);
U.S. Cl.
CPC ...
Abstract

A substrate via structure for stacked vias in a substrate/chip assembly includes: a center via stack and a plurality of stacked vias clustered around the center via stack. In this structure, the center via and the surrounding vias are made of copper. Some of the surrounding vias may be non-functional vias and these may be of a different height than the functional vias.


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