The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 07, 2012
Filed:
Jun. 03, 2009
Su-chen Lai, Hsinchu, TW;
Ming-yuan Wu, Hsinchu, TW;
Kong-beng Thei, Hsin-Chu, TW;
Harry Hak-lay Chuang, Hsin-Chu, TW;
Chiung-han Yeh, Tainan, TW;
Hong-dyi Chang, Taipei, TW;
Kuo Cheng Cheng, Baoshan Township, Hsinchu County, TW;
Chien-hung Wu, Tainan, TW;
Tzung-chi Lee, Banciao, TW;
Su-Chen Lai, Hsinchu, TW;
Ming-Yuan Wu, Hsinchu, TW;
Kong-Beng Thei, Hsin-Chu, TW;
Harry Hak-Lay Chuang, Hsin-Chu, TW;
Chiung-Han Yeh, Tainan, TW;
Hong-Dyi Chang, Taipei, TW;
Kuo Cheng Cheng, Baoshan Township, Hsinchu County, TW;
Chien-Hung Wu, Tainan, TW;
Tzung-Chi Lee, Banciao, TW;
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Abstract
A semiconductor device is provided which includes a semiconductor substrate having a first portion and a second portion, transistors formed in the first portion of the substrate, each transistor having a gate structure with a high-k dielectric and a metal gate, a device element formed in the second portion of the substrate, the device element being isolated by an isolation region, and a polishing stopper formed adjacent the isolation region and having a surface that is substantially planar with a surface of the gate structures of the transistors in the first region.