The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 07, 2012
Filed:
Jul. 29, 2009
Method of fabricating a device using low temperature anneal processes, a device and design structure
Anthony G. Domenicucci, New Paltz, NY (US);
Terence L. Kane, Wappinger Falls, NY (US);
Shreesh Narasimha, Beacon, NY (US);
Karen A. Nummy, Hopewell Junction, NY (US);
Viorel Ontalus, Hopewell Junction, NY (US);
Yun-yu Wang, Poughquag, NY (US);
Anthony G. Domenicucci, New Paltz, NY (US);
Terence L. Kane, Wappinger Falls, NY (US);
Shreesh Narasimha, Beacon, NY (US);
Karen A. Nummy, Hopewell Junction, NY (US);
Viorel Ontalus, Hopewell Junction, NY (US);
Yun-Yu Wang, Poughquag, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A method of fabricating a device using a sequence of annealing processes is provided. More particularly, a logic NFET device fabricated using a low temperature anneal to eliminate dislocation defects, method of fabricating the NFET device and design structure is shown and described. The method includes forming a stress liner over a gate structure and subjecting the gate structure and stress liner to a low temperature anneal process to form a stacking force in single crystalline silicon near the gate structure as a way to memorized the stress effort. The method further includes stripping the stress liner from the gate structure and performing an activation anneal at high temperature on device.