The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 24, 2012
Filed:
Nov. 19, 2009
Max Levy, Essex Junction, NY (US);
Natalie Feilchenfeld, Essex Junction, NY (US);
Richard Phelps, Essex Junction, NY (US);
Bethann Rainey, Essex Junction, NY (US);
James Slinkman, Essex Junction, NY (US);
Steven H. Voldman, Essex Junction, NY (US);
Michael Zierak, Essex Junction, NY (US);
Hubert Enichlmair, Graz, AT;
Martin Knaipp, Unterpremstaetten, AT;
Bernard Loeffler, Gleisdorf, AT;
Rainer Minixhofer, Unterpremstaetten, AT;
Jong-mun Park, Graz, AT;
Georg Roehrer, Graz, AT;
Max Levy, Essex Junction, NY (US);
Natalie Feilchenfeld, Essex Junction, NY (US);
Richard Phelps, Essex Junction, NY (US);
BethAnn Rainey, Essex Junction, NY (US);
James Slinkman, Essex Junction, NY (US);
Steven H. Voldman, Essex Junction, NY (US);
Michael Zierak, Essex Junction, NY (US);
Hubert Enichlmair, Graz, AT;
Martin Knaipp, Unterpremstaetten, AT;
Bernard Loeffler, Gleisdorf, AT;
Rainer Minixhofer, Unterpremstaetten, AT;
Jong-Mun Park, Graz, AT;
Georg Roehrer, Graz, AT;
International Business Machines Corporation, Armonk, NY (US);
Abstract
A method of forming an isolation region is provided that in one embodiment substantially reduces divot formation. In one embodiment, the method includes providing a semiconductor substrate, forming a first pad dielectric layer on an upper surface of the semiconductor substrate and forming a trench through the first pad dielectric layer into the semiconductor substrate. In a following process sequence, the first pad dielectric layer is laterally etched to expose an upper surface of the semiconductor substrate that is adjacent the trench, and the trench is filled with a trench dielectric material, wherein the trench dielectric material extends atop the upper surface of the semiconductor substrate adjacent the trench and abuts the pad dielectric layer.