The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 10, 2012
Filed:
Jul. 23, 2010
Zhiwei Gong, Chandler, AZ (US);
Scott M. Hayes, Chandler, AZ (US);
George R. Leal, Cedar Park, TX (US);
Douglas G. Mitchell, Tempe, AZ (US);
Jason R. Wright, Chandler, AZ (US);
Jianwen Xu, Chandler, AZ (US);
Zhiwei Gong, Chandler, AZ (US);
Scott M. Hayes, Chandler, AZ (US);
George R. Leal, Cedar Park, TX (US);
Douglas G. Mitchell, Tempe, AZ (US);
Jason R. Wright, Chandler, AZ (US);
Jianwen Xu, Chandler, AZ (US);
Freescale Semiconductor, Inc., Austin, TX (US);
Abstract
A method is used to form a packaged semiconductor device. A semiconductor device, which has an active surface, is placed in an opening of a circuit board. The circuit board has a first major surface and a second major surface having the opening, first vias that extend between the first major surface and the second major surface, first contact pads terminating the vias at the first major surface, and second contact pads terminating the vias at the second major surface. A dielectric layer is applied over the semiconductor device and the second major surface of the circuit board. An interconnect layer is formed over the dielectric layer. The interconnect layer has second vias electrically connected to the second contact pads, third vias that are electrically connected to the active surface of the semiconductor device, an exposed surface, and third contact pads at the exposed surface.