The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 12, 2012
Filed:
Jul. 10, 2008
Timothy J. Dalton, Ridgefield, CT (US);
Wesley C. Natzle, New Paltz, NY (US);
Paul W. Pastel, Essex Junction, VT (US);
Richard S. Wise, New Windsor, NY (US);
Hongwen Yan, Somers, NY (US);
Ying Zhang, Yorktown Heights, NY (US);
Timothy J. Dalton, Ridgefield, CT (US);
Wesley C. Natzle, New Paltz, NY (US);
Paul W. Pastel, Essex Junction, VT (US);
Richard S. Wise, New Windsor, NY (US);
Hongwen Yan, Somers, NY (US);
Ying Zhang, Yorktown Heights, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A chemical composition and method for providing uniform and consistent etching of gate stacks on a semiconductor wafer, whereby the composition includes an etchant and an added ballast gas added. The gate stacks are formed using this combined etchant and ballast gas composition. The ballast gas may either be similar to, or the equivalent of, a gaseous byproduct generated within the processing chamber. The ballast gas is added in either an overload amount, or in an amount sufficient to compensate for varying pattern factor changes across the water. This etchant and added ballast gas form a substantially homogeneous etchant across the entire wafer, thereby accommodating for or compensating for these pattern factor differences. When etching the wafer using this homogeneous etchant, a passivation layer is formed on exposed wafer surfaces. The passivation layer protects the lateral sidewalls of the gate stacks during etch to result in straighter gate stacks.