The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 05, 2012
Filed:
Oct. 18, 2010
Chih-hao Yu, Tainan County, TW;
Li-wei Cheng, Hsinchu, TW;
Che-hua Hsu, Hsinchu County, TW;
Tian-fu Chiang, Taipei, TW;
Cheng-hsien Chou, Tainan, TW;
Chien-ming Lai, Tainan County, TW;
Yi-wen Chen, Tainan County, TW;
Chien-ting Lin, Hsinchu, TW;
Guang-hwa MA, Hsinchu, TW;
Chih-Hao Yu, Tainan County, TW;
Li-Wei Cheng, Hsinchu, TW;
Che-Hua Hsu, Hsinchu County, TW;
Tian-Fu Chiang, Taipei, TW;
Cheng-Hsien Chou, Tainan, TW;
Chien-Ming Lai, Tainan County, TW;
Yi-Wen Chen, Tainan County, TW;
Chien-Ting Lin, Hsinchu, TW;
Guang-Hwa Ma, Hsinchu, TW;
United Microelectronics Corp., Science-Based Industrial Park, Hsin-Chu, TW;
Abstract
A method for fabricating a semiconductor structure is disclosed. A substrate with a first transistor having a first dummy gate and a second transistor having a second dummy gate is provided. The conductive types of the first transistor and the second transistor are different. The first and second dummy gates are simultaneously removed to form respective first and second openings. A high-k dielectric layer, a second type conductive layer and a first low resistance conductive layer are formed on the substrate and fill in the first and second openings, with the first low resistance conductive layer filling up the second opening. The first low resistance conductive layer and the second type conductive layer in the first opening are removed. A first type conductive layer and a second low resistance conductive layer are then formed in the first opening, with the second low resistance conductive layer filling up the first opening.