The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 17, 2012

Filed:

Apr. 29, 2011
Applicants:

Mou-shiung Lin, Hsin-Chu, TW;

Chiu-ming Chou, Kao-Hsiung, TW;

Chien-kang Chou, Tainan County, TW;

Hsin-jung Lo, Taipei County, TW;

Inventors:

Mou-Shiung Lin, Hsin-Chu, TW;

Chiu-Ming Chou, Kao-Hsiung, TW;

Chien-Kang Chou, Tainan County, TW;

Hsin-Jung Lo, Taipei County, TW;

Assignee:

Megica Corporation, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/40 (2006.01);
U.S. Cl.
CPC ...
Abstract

A semiconductor chip includes first, second and third metal interconnects and an insulating layer over a semiconductor substrate. First, second and third openings in the insulating layer are over first, second and third contact points of the first, second and third metal interconnects, respectively. A fourth metal interconnect over the insulating layer connects the first and second contact points. The fourth metal interconnect includes a first metal layer and a second metal layer. The first metal layer is under but not at a sidewall of the second metal layer. The semiconductor chip includes a metal bump connected to the third contact point through the third opening, and a dielectric layer over the fourth metal interconnect and the insulating layer. No opening is in the dielectric layer on the fourth metal interconnect, and the metal bump has a top higher than a top surface of the dielectric layer.


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