The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 17, 2012

Filed:

May. 13, 2008
Applicants:

Douglas D. Coolbaugh, Highland, NY (US);

Ebenezer E. Eshun, Newburgh, NY (US);

Ephrem G. Gebreselasie, South Burlington, VT (US);

Zhong-xiang He, Essex Junction, VT (US);

Herbert Lei Ho, New Windsor, NY (US);

Deok-kee Kim, Bedford Hills, NY (US);

Chandrasekharan Kothandaraman, Hopewell Junction, NY (US);

Dan Moy, Bethel, CT (US);

Robert Mark Rassel, Colchester, VT (US);

John Matthew Safran, Wappingers Falls, NY (US);

Kenneth Jay Stein, Sandy Hook, CT (US);

Norman Whitelaw Robson, Hopewell Junction, NY (US);

Ping-chuan Wang, Hopewell Junction, NY (US);

Hongwen Yan, Somers, NY (US);

Inventors:

Douglas D. Coolbaugh, Highland, NY (US);

Ebenezer E. Eshun, Newburgh, NY (US);

Ephrem G. Gebreselasie, South Burlington, VT (US);

Zhong-Xiang He, Essex Junction, VT (US);

Herbert Lei Ho, New Windsor, NY (US);

Deok-kee Kim, Bedford Hills, NY (US);

Chandrasekharan Kothandaraman, Hopewell Junction, NY (US);

Dan Moy, Bethel, CT (US);

Robert Mark Rassel, Colchester, VT (US);

John Matthew Safran, Wappingers Falls, NY (US);

Kenneth Jay Stein, Sandy Hook, CT (US);

Norman Whitelaw Robson, Hopewell Junction, NY (US);

Ping-Chuan Wang, Hopewell Junction, NY (US);

Hongwen Yan, Somers, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A semiconductor structure and a method for fabricating the semiconductor structure provide a field effect device located and formed upon an active region of a semiconductor substrate and at least one of a fuse structure, an anti-fuse structure and a resistor structure located and formed at least in part simultaneously upon an isolation region laterally separated from the active region within the semiconductor substrate. The field effect device includes a gate dielectric comprising a high dielectric constant dielectric material and a gate electrode comprising a metal material. The at least one of the fuse structure, anti-fuse structure and resistor structure includes a pad dielectric comprising the same material as the gate dielectric, and optionally, also a fuse, anti-fuse or resistor that may comprise the same metal material as the gate electrode.


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