The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 03, 2012

Filed:

Feb. 19, 2009
Applicants:

Thomas E. Grebs, Mountaintop, PA (US);

Mark Rinehimer, Mountaintop, PA (US);

Joseph Yedinak, Mountaintop, PA (US);

Dean E. Probst, West Jordan, UT (US);

Gary Dolny, Mountaintop, PA (US);

John Benjamin, Mountaintop, PA (US);

Inventors:

Thomas E. Grebs, Mountaintop, PA (US);

Mark Rinehimer, Mountaintop, PA (US);

Joseph Yedinak, Mountaintop, PA (US);

Dean E. Probst, West Jordan, UT (US);

Gary Dolny, Mountaintop, PA (US);

John Benjamin, Mountaintop, PA (US);

Assignee:

Fairchild Semiconductor Corporation, South Portland, ME (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/02 (2006.01); H01L 21/332 (2006.01);
U.S. Cl.
CPC ...
Abstract

Various structures and methods for improving the performance of trench-shielded power semiconductor devices and the like are described. An exemplary device comprises a semiconductor region having a surface, a first area of the semiconductor region, a well region of a first conductivity type disposed in the semiconductor region and around the first area, and a plurality of trenches extending in a semiconductor region. Each trench haves a first end disposed in a first portion of the well region, a second end disposed in a second portion of the well region, and a middle portion between the first and second ends and disposed in the first area. Each trench further having opposing sidewalls lined with a dielectric layer, and a conductive electrode disposed on at least a portion of the dielectric layer.


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