The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 03, 2012
Filed:
Oct. 19, 2009
Khee Yong Lim, Singapore, SG;
Victor Chan, Newburgh, NY (US);
Eng Hua Lim, Singapore, SG;
Wenhe Lin, Singapore, SG;
Jamin F. Fen, Wappingers Falls, NY (US);
Khee Yong Lim, Singapore, SG;
Victor Chan, Newburgh, NY (US);
Eng Hua Lim, Singapore, SG;
Wenhe Lin, Singapore, SG;
Jamin F. Fen, Wappingers Falls, NY (US);
Abstract
A method for forming a device with both PFET and NFET transistors using a PFET compressive etch stop liner and a NFET tensile etch stop liner and two anneals in a deuterium containing atmosphere. The method comprises: providing a NFET transistor in a NFET region and a PFET transistor in a PFET region. We form a NFET tensile contact etch-stop liner over the NFET region. Then we perform a first deuterium anneal. We form a PFET compressive etch stop liner over the PFET region. We form a (ILD) dielectric layer with contact openings over the substrate. We perform a second deuterium anneal. The temperature of the second deuterium anneal is less than the temperature of the first deuterium anneal.