The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 20, 2012

Filed:

Oct. 24, 2008
Applicants:

Takashi Noguchi, Machida, JP;

Shigetoshi Sameshima, Machida, JP;

Shigeki Kurihara, Hitachinaka, JP;

Tamao Ishikawa, Hitachinaka, JP;

Yutaka Tandai, Hitachinaka, JP;

Inventors:

Takashi Noguchi, Machida, JP;

Shigetoshi Sameshima, Machida, JP;

Shigeki Kurihara, Hitachinaka, JP;

Tamao Ishikawa, Hitachinaka, JP;

Yutaka Tandai, Hitachinaka, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06K 9/62 (2006.01);
U.S. Cl.
CPC ...
Abstract

There is provided an evaluation object pattern determining apparatus capable of determining local patterns to be evaluated. The apparatus is for use in a pattern evaluating system storing patterns of a LSI chip as CAD data, picking out coordinates of local patterns whose process margin is small from the CAD data by way of simulation and assisting observation of the local patterns produced in a fabrication line. The apparatus includes a risk level map creating section for creating risk level maps in which risk areas are disposed. The risk area is assigned with a risk level obtained by digitizing that the risk area is an area whose process margin is smaller than other areas. The apparatus also includes a superimposition processing section for superimposing the coordinates of the local patterns with the risk level map to pick out the coordinates of the local patterns located within the risk area.


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