The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 13, 2012
Filed:
Jun. 17, 2009
Mark a Gerber, Lucas, TX (US);
Kurt P Wachtler, Richardson, TX (US);
Abram M. Castro, Fort Worth, TX (US);
Mark A Gerber, Lucas, TX (US);
Kurt P Wachtler, Richardson, TX (US);
Abram M. Castro, Fort Worth, TX (US);
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
A semiconductor system () of one or more semiconductor interposers () with a certain dimension (), conductive vias () extending from the first to the second surface, with terminals and attached non-reflow metal studs () at the ends of the vias. A semiconducting interposer surface may include discrete electronic components or an integrated circuit. One or more semiconductor chips () have a dimension () narrower than the interposer dimension, and an active surface with terminals and non-reflow metal studs (). One chip is flip-attached to the first interposer surface, and another chip to the second interposer surface, so that the interposer dimension projects over the chip dimension. An insulating substrate () has terminals and reflow bodies () to connect to the studs of the projecting interposer.