The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 06, 2012

Filed:

Jun. 29, 2009
Applicants:

Hem Takiar, Fremont, CA (US);

Cheeman Yu, Madison, WI (US);

Ken Jian Ming Wang, San Francisco, CA (US);

Chin-tien Chiu, Taichung, TW;

Han-shiao Chen, Taichung County, TW;

Chih-chin Liao, Changhua, TW;

Inventors:

Hem Takiar, Fremont, CA (US);

Cheeman Yu, Madison, WI (US);

Ken Jian Ming Wang, San Francisco, CA (US);

Chin-Tien Chiu, Taichung, TW;

Han-Shiao Chen, Taichung County, TW;

Chih-Chin Liao, Changhua, TW;

Assignee:

SanDisk Technologies Inc., Plano, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/44 (2006.01);
U.S. Cl.
CPC ...
Abstract

A strengthened semiconductor die substrate and package are disclosed. The substrate may include contact fingers formed with nonlinear edges. Providing a nonlinear contour to the contact finger edges reduces the mechanical stress exerted on the semiconductor die which would otherwise occur with straight edges to the contact fingers. The substrate may additionally or alternatively include plating traces extending at an angle from the contact fingers. Extending at an angle, at least the ends of the plating traces at the edge of the substrate are covered beneath a lid in which the semiconductor package is encased. Thus, when in use with a host device, contact between the ends of the plating traces beneath the lid and contact pins of the host device is avoided.


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