The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 14, 2012
Filed:
Jan. 31, 2008
James Douglas Warnock, Somers, NY (US);
Wendel Dieter, Schoenaich, DE;
David E. Lackey, Jericho, VT (US);
William Vincent Huott, Holmes, NY (US);
Leon Jacob Sigal, Monsey, NY (US);
Louis Bernard Bushard, Rochester, MN (US);
Sang Hoo Dhong, San Jose, CA (US);
James Douglas Warnock, Somers, NY (US);
Wendel Dieter, Schoenaich, DE;
David E. Lackey, Jericho, VT (US);
William Vincent Huott, Holmes, NY (US);
Leon Jacob Sigal, Monsey, NY (US);
Louis Bernard Bushard, Rochester, MN (US);
Sang Hoo Dhong, San Jose, CA (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A method, system and program are provided for generating level sensitive scan design (LSSD) clock signals from a general scan design (GSD) clock buffer using an intermediate clock signal and one or more first mode control signals to generate a plurality of LSSD clock signals from an output section of the GSD clock buffer that receives the intermediate clock signal and the first mode control signal(s), where the GSD clock buffer is also configured to generate a plurality of GSD clock signals in response to receiving a GSD mode, generating an intermediate clock signal from the input section of the GSD clock buffer in response receiving a GSD mode signal.