The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 31, 2012

Filed:

May. 26, 2011
Applicants:

Akinori Shiraishi, Nagano, JP;

Kei Murayama, Nagano, JP;

Yuichi Taguchi, Nagano, JP;

Masahiro Sunohara, Nagano, JP;

Mitsutoshi Higashi, Nagano, JP;

Inventors:

Akinori Shiraishi, Nagano, JP;

Kei Murayama, Nagano, JP;

Yuichi Taguchi, Nagano, JP;

Masahiro Sunohara, Nagano, JP;

Mitsutoshi Higashi, Nagano, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/49 (2006.01);
U.S. Cl.
CPC ...
Abstract

In a silicon substrate for a package, a through electrode is provided with which a through hole passing through from a bottom surface of a cavity for accommodating a chip of an electronic device to a back surface of the substrate is filled. An end part of the through electrode in the bottom surface side of the cavity has a connection part to a wiring that forms an electric circuit including the chip of the electronic device. The silicon substrate for a package is characterized in that (1) a thin film wiring is included as the wiring and the connection part is reinforced by a conductor connected to the thin film wiring and/or (2) a wire bonding part is included as the wiring and the connection part is formed by wire bonding the end part of the through electrode in the bottom surface side of the cavity.


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