The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 24, 2012
Filed:
Sep. 30, 2009
Anindya Poddar, Sunnyvale, CA (US);
Nghia Thuc Tu, San Jose, CA (US);
Jaime Bayan, San Francisco, CA (US);
Will Wong, Belmont, CA (US);
David Chin, Cupertino, CA (US);
Anindya Poddar, Sunnyvale, CA (US);
Nghia Thuc Tu, San Jose, CA (US);
Jaime Bayan, San Francisco, CA (US);
Will Wong, Belmont, CA (US);
David Chin, Cupertino, CA (US);
National Semiconductor Corporation, Santa Clara, CA (US);
Abstract
The present inventions relate to methods and arrangements for using a thin foil to form electrical interconnects in an integrated circuit package. One embodiment of the present invention involves attaching multiple dice to a foil carrier structure. The foil carrier structure is made of a thin foil that is bonded to a carrier. The dice and at least a portion of the metallic foil is then encapsulated with a molding material. The carrier is removed, leaving behind a molded foil structure. The exposed foil is patterned and etched using photolithographic techniques to define multiple device areas in the foil. Each device area includes multiple conductive lines. Afterwards, portions of the conductive lines are covered with a dielectric material and other portions are left exposed to define multiple bond pads in the device area. The molded foil structure can be singulated to form multiple integrated circuit packages.