The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 03, 2012
Filed:
Jul. 21, 2010
Cha-jea JO, Suwon-si, KR;
Myung-kee Chung, Cheonan-si, KR;
Nam-seog Kim, Yongin-si, KR;
In-young Lee, Yongin-si, KR;
Seok-ho Kim, Bucheon-si, KR;
Ho-jin Lee, Seoul, KR;
Ju-il Choi, Suwon-si, KR;
Chang-woo Shin, Yongin-si, KR;
Cha-Jea Jo, Suwon-si, KR;
Myung-Kee Chung, Cheonan-si, KR;
Nam-Seog Kim, Yongin-si, KR;
In-Young Lee, Yongin-si, KR;
Seok-Ho Kim, Bucheon-si, KR;
Ho-Jin Lee, Seoul, KR;
Ju-Il Choi, Suwon-si, KR;
Chang-Woo Shin, Yongin-si, KR;
Abstract
A chip stack package includes a substrate, a plurality of chips, a plurality of adhesive layers and a plug. The substrate has a wiring pattern and a seed layer formed on the wiring pattern. Each of the chips has an electrode pad and a first through-hole that penetrates the electrode pad. The chips are stacked such that the first through-holes are aligned on the seed layer of the substrate. The adhesive layers are interposed between the substrate and one of the chips, as well as between the chips. Each of the adhesive layers has a second through-hole connected to the first through-hole. The plug fills up the first through-holes and the second through-holes and electrically connects the electrode pads to the wiring pattern of the substrate. A cross-sectional area of the plug in the second through-holes may be larger than that of the plug in the first through-holes.