The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 03, 2012
Filed:
Dec. 02, 2009
Robert L. Hsieh, Los Altos, CA (US);
Khiem Nguyen, San Jose, CA (US);
Warren W. Flack, San Jose, CA (US);
Andrew M. Hawryluk, Los Altos, CA (US);
Robert L. Hsieh, Los Altos, CA (US);
Khiem Nguyen, San Jose, CA (US);
Warren W. Flack, San Jose, CA (US);
Andrew M. Hawryluk, Los Altos, CA (US);
Ultratech, Inc., San Jose, CA (US);
Abstract
A method of aligning a wafer when lithographically fabricating a light-emitting diode (LED). The method includes forming on the wafer at least one roughened alignment mark having a root-mean-square (RMS) surface roughness σ. The roughened alignment mark is formed as a consequence of forming a plasma etch to roughen a LED surface on which the wafer alignment mark resides. The method also includes imaging the at least one roughened wafer alignment mark with alignment light having a wavelength λthat is in the range from about 2σto about 8σ. The method also includes comparing the detected image to an alignment reference to establish wafer alignment. Once wafer alignment is established, p-contacts and n-contacts can be formed on the LED upper surface in their proper locations.