The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 27, 2011
Filed:
Sep. 11, 2008
Chih-hao Yu, Tainan County, TW;
Li-wei Cheng, Hsin-Chu, TW;
Che-hua Hsu, Hsin-Chu Hsien, TW;
Cheng-hsien Chou, Tainan, TW;
Tian-fu Chiang, Taipei, TW;
Chien-ming Lai, Tainan County, TW;
Yi-wen Chen, Tainan County, TW;
Jung-tsung Tseng, Tainan, TW;
Chien-ting Lin, Hsin-Chu, TW;
Guang-hwa MA, Hsinchu, TW;
Chih-Hao Yu, Tainan County, TW;
Li-Wei Cheng, Hsin-Chu, TW;
Che-Hua Hsu, Hsin-Chu Hsien, TW;
Cheng-Hsien Chou, Tainan, TW;
Tian-Fu Chiang, Taipei, TW;
Chien-Ming Lai, Tainan County, TW;
Yi-Wen Chen, Tainan County, TW;
Jung-Tsung Tseng, Tainan, TW;
Chien-Ting Lin, Hsin-Chu, TW;
Guang-Hwa Ma, Hsinchu, TW;
United Microelectronics Corp., Science-Based Industrial Park, Hsin-Chu, TW;
Abstract
A method for fabricating metal gate transistor is disclosed. First, a substrate having a first transistor region and a second transistor region is provided. Next, a stacked film is formed on the substrate, in which the stacked film includes at least one high-k dielectric layer and a first metal layer. The stacked film is patterned to form a plurality of gates in the first transistor region and the second transistor region, a dielectric layer is formed on the gates, and a portion of the dielectric layer is planarized until reaching the top of each gates. The first metal layer is removed from the gate of the second transistor region, and a second metal layer is formed over the surface of the dielectric layer and each gate for forming a plurality of metal gates in the first transistor region and the second transistor region.