The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 13, 2011
Filed:
Feb. 13, 2009
Shenqing Fang, Fremont, CA (US);
Chun Chen, San Jose, CA (US);
Wenmei LI, San Jose, CA (US);
Inkuk Kang, San Jose, CA (US);
Gang Xue, Sunnyvale, CA (US);
Hyesook Hong, Allen, TX (US);
Shenqing Fang, Fremont, CA (US);
Chun Chen, San Jose, CA (US);
Wenmei Li, San Jose, CA (US);
Inkuk Kang, San Jose, CA (US);
Gang Xue, Sunnyvale, CA (US);
Hyesook Hong, Allen, TX (US);
Spansion LLC, Sunnyvale, CA (US);
Abstract
A memory and method of manufacture employing word line scaling. A layered stack, including a charge trapping component and a core polysilicon layer, is formed on a core section and a peripheral section of a substrate. A portion of the layered stack, including the core polysilicon layer is then removed from the peripheral section. A peripheral polysilicon layer, which is thicker than the core polysilicon layer of the layered stack, is next formed on the layered stack and the peripheral section. The layered stack is then isolated from the peripheral polysilicon layer by removing a portion of the peripheral polysilicon layer from the core section, and polysilicon lines are patterned in the isolated layered stack.