The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 13, 2011
Filed:
May. 18, 2010
Chu-yin Tseng, Tainan County, TW;
Shih-chieh Hsu, Hsinchu, TW;
Chih-chiang Wu, Taichung County, TW;
Shyh-fann Ting, Tai-Nan, TW;
Po-lun Cheng, Kao-Hsiung Hsien, TW;
Hsuan-hsu Chen, Tai-Nan, TW;
Chu-Yin Tseng, Tainan County, TW;
Shih-Chieh Hsu, Hsinchu, TW;
Chih-Chiang Wu, Taichung County, TW;
Shyh-Fann Ting, Tai-Nan, TW;
Po-Lun Cheng, Kao-Hsiung Hsien, TW;
Hsuan-Hsu Chen, Tai-Nan, TW;
United Microelectronics Corp., Science-Based Industrial Park, Hsin-Chu, TW;
Abstract
A method of fabricating a MOS transistor is disclosed. The method includes the steps of: providing a semiconductor substrate; forming at least a gate on the semiconductor substrate; forming a protective layer on the semiconductor substrate, and the protective layer covering the surface of the gate; forming at least a recess within the semiconductor substrate adjacent to the gate; forming an epitaxial layer in the recess, wherein the top surface of the epitaxial layer is above the surface of the semiconductor substrate; and forming a spacer on the sidewall of the gate and on a portion of the epitaxial layer, wherein a contact surface of the epitaxial layer and the spacer is above the surface of the semiconductor substrate.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile