The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 06, 2011

Filed:

Mar. 26, 2009
Applicants:

Yuki Niyama, Tokyo, JP;

Seikoh Yoshida, Tokyo, JP;

Hiroshi Kambayashi, Tokyo, JP;

Takehiko Nomura, Tokyo, JP;

Masayuki Iwami, Kanagawa, JP;

Shinya Ootomo, Tokyo, JP;

Inventors:

Yuki Niyama, Tokyo, JP;

Seikoh Yoshida, Tokyo, JP;

Hiroshi Kambayashi, Tokyo, JP;

Takehiko Nomura, Tokyo, JP;

Masayuki Iwami, Kanagawa, JP;

Shinya Ootomo, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
Abstract

A field effect transistor formed of a semiconductor of a III group nitride compound, includes an electron running layer formed on a substrate and formed of GaN; an electron supplying layer formed on the electron running layer and formed of AlGaN (0.01≦x≦0.4), the electron supplying layer having a band gap energy different from that of the electron running layer and being separated with a recess region having a depth reaching the electron running layer; a source electrode and a drain electrode formed on the electron supplying layer with the recess region in between; a gate insulating film layer formed on the electron supplying layer for covering a surface of the electron running layer in the recess region; and a gate electrode formed on the gate insulating film layer in the recess region. The electron supplying layer has a layer thickness between 5.5 nm and 40 nm.


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