The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 01, 2011
Filed:
Jul. 14, 2009
Jean-marie Brunet, San Jose, CA (US);
William S. Graupp, Aurora, OR (US);
Jean-Marie Brunet, San Jose, CA (US);
William S. Graupp, Aurora, OR (US);
Mentor Graphics Corporation, Wilsonville, OR (US);
Abstract
In one embodiment, a method for determining a contour simplification of an object for a simulation is provided. An object in a layout of a transistor design to be created with the photolithographic process is determined. The object includes a width and a length in the layout. A contour simulation is performed to determine a generated contour object. The contour simulation simulates parametric variation factors that may occur in the photolithographic process. An adjusted width and adjusted length of the object is then determined based on the generated contour object. The adjusted width and the adjusted length are usable to determine a parametric model for simulation of the object. For example, a layout versus schematic (LVS) tool may back-annotate the layout. Then, a SPICE simulation may use the output of the LVS tool to verify the electrical behavior of the transistor using the adjusted width and adjusted length.