The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 04, 2011
Filed:
Jan. 12, 2010
Bong-seok Seo, Hwaseong-si, KR;
Jong-ho Yang, SengNam, KR;
Dong Hee Yu, Whasung, KR;
O Sung Kwon, Wappingers Falls, NY (US);
Oh-jung Kwon, Hopewell Junction, NY (US);
Bong-Seok Seo, Hwaseong-si, KR;
Jong-Ho Yang, SengNam, KR;
Dong Hee Yu, Whasung, KR;
O Sung Kwon, Wappingers Falls, NY (US);
Oh-Jung Kwon, Hopewell Junction, NY (US);
Samsung Electronics Co., Ltd., Suwon-Si, KR;
International Business Machines Corporation, Armonk, NY (US);
Infineon Technologies AG, Neubiberg, DE;
Abstract
A method of transistor formation using a capping layer in complimentary metal-oxide semiconductor (CMOS) structures is provided, the method including: depositing a conductive layer over an n-type field effect transistor (nFET) and over a p-type field effect transistor (pFET); depositing a capping layer directly over the conductive layer; etching the capping and conductive layers to form a capped gate conductor to gates of the nFET and pFET, respectively; ion-implanting the nFET transistor with a first dopant; and ion-implanting the pFET transistor with a second dopant, wherein ion-implanting a transistor substantially dopes its source and drain regions, but not its gate region.