Interconnection modeling for semiconductor fabrication process effects

Abstract

In one embodiment, an interconnect object in a layout of an integrated circuit design to be created with a photolithographic process is determined. The interconnect object includes a width and a length in the layout. A contour generation of the interconnect object in a drawn design is determined based on processing variation factors for the photolithographic process, which produces a generated contour object. A plurality of segments in the generated contour object may be determined based on processing variations. Segments are then broken up based on the processing variations that result. An adjusted width and adjusted length for each of the plurality of segments of the generated contour object are then determined. Resistances and capacitances may be extracted using the adjusted widths and adjusted lengths. Then, the output of the LVS tool may be sent to a SPICE simulation to verify the electrical behavior of the interconnect.