The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 06, 2011
Filed:
Aug. 29, 2007
Thomas C. Roedle, Nijmegen, NL;
Elnar O. Sveinbjornsson, Gothenburg, SE;
Halldor O. Olafsson, Reykjavik, IS;
Gudjon I. Gudjonsson, Gothenburg, SE;
Carl F. Allerstam, Gothenburg, SE;
Thomas C. Roedle, Nijmegen, NL;
Elnar O. Sveinbjornsson, Gothenburg, SE;
Halldor O. Olafsson, Reykjavik, IS;
Gudjon I. Gudjonsson, Gothenburg, SE;
Carl F. Allerstam, Gothenburg, SE;
NXP B.V., Eindhoven, NL;
Abstract
A method of manufacturing a semiconductor device based on a SiC substrate involves forming an oxide layer on a Si-terminated face of the SiC substrate at an oxidation rate sufficiently high to achieve a near interface trap density below 5×10cm; and annealing the oxidized SiC substrate in a hydrogen-containing environment, to passivate deep traps formed in the oxide-forming step, thereby enabling manufacturing of a SiC-based MOSFET having improved inversion layer mobility and reduced threshold voltage. It has been found that the density of DTs increases while the density of NITs decreases when the Si-face of the SiC substrate is subject to rapid oxidation. The deep traps formed during the rapid oxidation can be passivated by hydrogen annealing, thus leading to a significantly decreased threshold voltage for a semiconductor device formed on the oxide.