The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 23, 2011

Filed:

Sep. 26, 2007
Applicants:

Kangguo Cheng, Beacon, NY (US);

Munir D. Naeem, Poughkeepsie, NY (US);

David M. Dobuzinsky, Hopewell Junction, NY (US);

Byeong Y. Kim, Lagrangeville, NY (US);

Inventors:

Kangguo Cheng, Beacon, NY (US);

Munir D. Naeem, Poughkeepsie, NY (US);

David M. Dobuzinsky, Hopewell Junction, NY (US);

Byeong Y. Kim, Lagrangeville, NY (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 21/4763 (2006.01);
U.S. Cl.
CPC ...
Abstract

A deep trench is formed in a semiconductor-on-insulator (SOI) substrate and a pad layer thereupon. A conductive trench fill region is formed in the deep trench. A planarizing material layer having etch selectivity relative to the pad layer is applied. A portion of the pad layer having an edge that is vertically coincident with a sidewall of the deep trench is exposed by lithographic means. Exposed portion of the pad layer are removed selective to the planarizing material layer, followed by removal of exposed portion of a semiconductor layer selective to the conductive trench fill region by an anisotropic etch. The planarizing material layer is removed and a shallow trench isolation structure having a lower sidewall that is self-aligned to an edge of the original deep trench is formed. Another shallow trench isolation structure may be formed outside the deep trench concurrently.


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