The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 23, 2011
Filed:
Feb. 04, 2010
Che-hua Hsu, Hsinchu County, TW;
Zhi-cheng Lee, Tainan, TW;
Cheng-guo Chen, Changhua County, TW;
Shao-hua Hsu, Taoyuan County, TW;
Che-Hua Hsu, Hsinchu County, TW;
Zhi-Cheng Lee, Tainan, TW;
Cheng-Guo Chen, Changhua County, TW;
Shao-Hua Hsu, Taoyuan County, TW;
United Microelectronics Corp., Science-Based Industrial Park, Hsin-Chu, TW;
Abstract
A method of fabricating an efuse structure, a resistor structure and a transistor structure. First, a work function metal layer, a polysilicon layer and a first hard mask layer are formed to cover a transistor region, a resistor region and an e-fuse region on a substrate. Then, the work function metal layer on the resistor region and the efuse region is removed by using a first photomask. Later, a gate, a resistor, an efuse are formed in the transistor region, the resistor region and the efuse region respectively. After that, a dielectric layer aligning with the top surface of the gate is formed. Later, the polysilicon layer in the gate is removed by taking a second hard mask as a mask to form a recess. Finally, a metal layer fills up the recess.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile